library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.processor_types.all;

entity registers is
	port (
		clock : in std_ulogic;
        reset : in std_ulogic;
        rw_sel : in std_ulogic;
        reg_select_1 : in bit5;
        reg_select_2 : in bit5;
        reg_write    : in bit5;
		in_value : in bit32;
        out_value_1 : out bit32;
        out_value_2 : out bit32
	);
end registers;

architecture arch_registers of registers is
	signal registers : registers32;
begin
	seq: process(clock, reset)
	begin
        if (reset = '1') then
            registers <= (others => (others => '0'));
            out_value_1 <= (others => '0');
            out_value_2 <= (others => '0');
		elsif (rising_edge(clock)) then
			if (rw_sel = '1') then
				if (reg_write /= "00000") then
					registers(to_integer(unsigned(reg_write))) <= in_value;
				end if;
            else
                out_value_1 <= registers(to_integer(unsigned(reg_select_1)));
                out_value_2 <= registers(to_integer(unsigned(reg_select_2)));
            end if;
		end if;
	end process;
	
end;
